Flip-Flops simulator

Interactive sequential logic circuits with real-time state visualization

Explore SR, JK, D, T flip-flops with clock signals and timing diagrams

Sequential Logic Circuit simulator

Current State: Q = 0, Q' = 1

State: RESET

Next: RESET

Clock: ↑

Timing Diagram

Characteristic Table

SR Flip-Flop

The SR flip-flop is a basic sequential logic circuit that can store one bit of information. It has Set and Reset inputs that control the output state.

Q(t+1) = S + R'Q(t)

Q'(t+1) = R + S'Q'(t)

Invalid state: S = R = 1

Interactive Controls

Clock Speed:

Slow Fast

Example Operations

operation Statistics

Clock Cycles

State Changes

Set Operations

Reset Operations